A fault avoidance approach with test set generation in combinational circuits using genetic algorithm

In this paper a stuck-at-fault avoidance approach in combinational VLSI circuits using genetic algorithm (GA) by comparing two complementary circuits has been proposed. Analysis of whole test set generation for a fault model helps to reduce the fault detection probability in combinational circuits. The GA proves to be a very helpful algorithm in finding the highest suitable number of test patterns in reference to most suitable solution for any problem. The paper focuses on detectability concept which is a way to find out the fault present in the circuit. Undetectability is a way to avoid the detected fault which is present in the circuit. In this paper we are taking the complementary circuit of reference fault model and analyzing the results for both circuits by generating test sets. In this paper results are obtained for single stuck-at-fault in the ISIS PROTEUS (C12) benchmark circuit. Experimental results showed that the genetic algorithm is helpful in findings the best method to avoid fault in terms of fault coverage and fitness factor.

[1]  Irith Pomeranz,et al.  Vector replacement to improve static-test compaction forsynchronous sequential circuits , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Xiaoming Yu,et al.  Sequential circuit ATPG using combinational algorithms , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Chung-Len Lee,et al.  A Two-Phase Fault Simulation Scheme for Sequential Circuits , 1998, J. Inf. Sci. Eng..

[4]  Irith Pomeranz,et al.  On maximizing the fault coverage for a given test length limit in a synchronous sequential circuit , 2004, IEEE Transactions on Computers.

[5]  Elizabeth M. Rudnick,et al.  Application of simple genetic algorithms to sequential circuit test generation , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[6]  Irith Pomeranz,et al.  A built-in self-test method for diagnosis of synchronous sequential circuits , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[7]  V. Amar,et al.  Diagnosis of Large Combinational Networks , 1967, IEEE Trans. Electron. Comput..

[8]  Michael S. Hsiao,et al.  Sequential circuit test generation using dynamic state traversal , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[9]  Irith Pomeranz,et al.  On improving a fault simulation based test generator for synchronous sequential circuits , 2001, Proceedings 10th Asian Test Symposium.

[10]  Enrico Macii,et al.  Multiple fault diagnosis in combinational networks , 1994, Proceedings of 1994 37th Midwest Symposium on Circuits and Systems.

[11]  Elizabeth M. Rudnick,et al.  A genetic algorithm framework for test generation , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  M. Ray Mercer,et al.  An Efficient Delay Test Generation System for , 1992 .

[13]  Elizabeth M. Rudnick,et al.  Diagnostic test generation for sequential circuits , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[14]  Charles E. Taylor.  Adaptation in Natural and Artificial Systems: An Introductory Analysis with Applications to Biology, Control, and Artificial Intelligence. Complex Adaptive Systems.John H. Holland , 1994 .

[15]  Dr. T. Meyyappan,et al.  Fault Detection and Test Minimization Methods for Combinational Circuits-A Survey , 2011 .

[16]  Michael S. Hsiao,et al.  Efficient Sequential Test Generation Based on Logic Simulation , 2002, IEEE Des. Test Comput..

[17]  Vijay Kumar,et al.  Generating Test Patterns for Multiple Fault Detection in VLSI Circuits using Genetic Algorithm , 2011 .

[18]  Kalyana Kantipudi,et al.  Minimizing N-Detect Tests for Combinational Circuits , 2007 .

[19]  Irith Pomeranz,et al.  TOV: Sequential Test Generation by Ordering of Test Vectors , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Michael S. Hsiao,et al.  Fast Static Compaction Algorithms for Sequential Circuit Test Vectors , 1999, IEEE Trans. Computers.

[21]  Lalit M. Patnaik,et al.  A Simulation-Based Test Generation Scheme Using Genetic Algorithms , 1993, The Sixth International Conference on VLSI Design.