A Novel Division Algorithm and Architectures for Parallel and Sequential Processing

A new algorithm for reducing the division operation to a series of smaller divisions is introduced. Partitioning the dividend into segments, we perform divisions, shifts, and accumulations taking into account the weight of dividend bits. Each partial division can be performed by any existing division algorithm. From an algorithmic point of view, computation analysis is performed in comparison with the existing algorithms. From an implementation point of view, since the division can be performed by any existing divider, the designer can choose the divider which best meets his specifications. Although the algorithm is presented for integer numbers, it can be easily generalized for fractions, since it is only a matter of representation. Two possible implementations of the algorithm, namely the sequential and parallel are derived, with several variations, allowing performance, cost, and cost/performance trade-offs. Exhaustive comparisons of the derived implementations with many existing implementations in terms of area cost, performance, and cost/performance are done. A plethora of alternative implementations can be derived due to a variable number of partitions.

[1]  Israel Koren Computer arithmetic algorithms , 1993 .

[2]  Keshab K. Parhi,et al.  Fast low-power shared division and square-root architecture , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[3]  Tomás Lang,et al.  Low-Power Divider , 1999, IEEE Trans. Computers.

[4]  James E. Robertson,et al.  Radix-16 Signed-Digit Division , 1990, IEEE Trans. Computers.

[5]  Amos R. Omondi,et al.  Computer Arithmetic Systems , 1994 .

[6]  Donald Ervin Knuth,et al.  The Art of Computer Programming , 1968 .

[7]  Behrooz Parhami,et al.  Computer arithmetic - algorithms and hardware designs , 1999 .

[8]  M. Ercegovac,et al.  Division and Square Root: Digit-Recurrence Algorithms and Implementations , 1994 .