A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM

A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nano-CMOS static random access memory (SRAM) is presented. A 45nm single-ended seven transistor SRAM is used as a case study. The SRAM is subjected to a dual-VTh assignment using a novel combined Design of Experiments and Integer Linear Programming (DOE-ILP) algorithm, resulting in 50.6% power reduction (including leakage) and 43.9% increase in the read SNM. The process variation analysis of the optimal SRAM carried out considering twelve device parameters shows the robustness of the design.

[1]  Yong-Bin Kim,et al.  A low leakage 9t sram cell for ultra-low power operation , 2008, GLSVLSI '08.

[2]  Masashi Horiguchi,et al.  Review and future prospects of low-voltage RAM circuits , 2003, IBM J. Res. Dev..

[3]  Saraju P. Mohanty,et al.  Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[4]  R. Keerthi,et al.  Stability and Static Noise Margin Analysis of Low-Power SRAM , 2008, 2008 IEEE Instrumentation and Measurement Technology Conference.

[5]  Sani R. Nassif,et al.  Statistical analysis of SRAM cell stability , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[6]  Shunsuke Okumura,et al.  A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme , 2009, 2009 10th International Symposium on Quality Electronic Design.

[7]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[8]  Massoud Pedram,et al.  Reducing the Sub-threshold and Gate-tunneling Leakage of SRAM Cells using Dual-Vt and Dual-Tox Assignment , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[9]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[10]  Kaushik Roy,et al.  Process variation tolerant SRAM array for ultra low voltage applications , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[11]  Azadeh Davoodi,et al.  Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[12]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Saraju P. Mohanty,et al.  Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[14]  Margaret J. Robertson,et al.  Design and Analysis of Experiments , 2006, Handbook of statistics.

[15]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[16]  Dhiraj K. Pradhan,et al.  A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies , 2008, 2008 IEEE International SOC Conference.

[17]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[18]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.