Variable precision in mathematical and scientific computing Proposal for an ICERM workshop

From its introduction in the 1980s, the IEEE-754 standard for floating-point arithmetic has ably served a wide range of users: mathematicians, computer scientists, physicists, chemists, biologists, social scientists and engineers. William Kahan, who led the development of this standard, later received the ACM Turing Award for this work. The initial standard specified 32-bit (“single”) and 64-bit (“double”) floating-point arithmetic, which were quickly adopted by processor vendors. Even today, the vast majority of numerical computations in research and engineering employ either IEEE single or IEEE double, typically one or the other exclusively in a single application. However, recent developments have exhibited the need for a broader range of precision levels, and variable precision within a single application. There are clear performance advantages to a variable precision framework: faster processing, better cache utilization, lower memory usage and lower long-term data storage. But effective usage of variable precision requires a more sophisticated mathematical framework, together with corresponding software tools and diagnostic facilities. At the low end, the explosive rise of graphics, artificial intelligence and machine learning has underscored the utility of reduced precision levels. Accordingly, an IEEE 16-bit “half” precision standard has been specified, with five exponent bits and ten mantissa bits. Many in the machine learning community are using the “bfloat16” format, which has eight exponent bits and seven mantissa bits. Hardware such as NVIDIA’s tensor core units can take advantage of these formats to significantly increase processing rates. At the same time, researchers in the high-performance computing (HPC) field, in a drive to achieve exascale computing, are also reconsidering their usage of numerical precision, since as