Abstract The ever increasing demand for high levels of integration and miniaturization has created new transistor nodes, shrunk redistribution line width/space, and driven a reduction in solder bump pitch. This has created the need for Fan-out packaging. This paper presents a novel Fan-out Wafer level package which does not require use of molding process or materials used typically in such packages. In this technique, silicon is used as the carrier material instead of molding compound. Advantages of silicon include good reliability, high thermal stability, and low cost. This novel Mold-free Fan-out package passes standard reliability tests including temperature cycling (TCT), Drop test (DT), and Convection reflow.