A 2.37-Gb/s 284.8 mW Rate-Compatible (491,3,6) LDPC-CC Decoder
暂无分享,去创建一个
Hsie-Chia Chang | Chen-Yi Lee | Yu-Hsiang Lin | Chih-Lung Chen | Yu-Hsiang Lin | Chen-Yi Lee | Hsie-Chia Chang | Chih-Lung Chen
[1] Michael Lentmaier,et al. Reduced complexity decoding strategies for LDPC convolutional codes , 2004, International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings..
[2] Bruce F. Cockburn,et al. A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[3] Stephen Bates,et al. A memory-based architecture for FPGA implementations of low-density parity-check convolutional decoders , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[4] Ajay Dholakia,et al. Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.
[5] S. Bates,et al. High Throughput Parallel Decoder Design for LDPC Convolutional Codes , 2008, 2008 4th IEEE International Conference on Circuits and Systems for Communications.
[6] Gerhard Fettweis,et al. A High-Throughput Programmable Decoder for LDPC Convolutional Codes , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).
[7] Shyh-Jye Jou,et al. A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications , 2010, 2010 IEEE Asian Solid-State Circuits Conference.
[8] Xiaoyang Zeng,et al. An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $\mu$m CMOS , 2011, IEEE Journal of Solid-State Circuits.
[9] Kamil Sh. Zigangirov,et al. Time-varying periodic convolutional codes with low-density parity-check matrix , 1999, IEEE Trans. Inf. Theory.
[10] Michael Lentmaier,et al. Implementation aspects of LDPC convolutional codes , 2008, IEEE Transactions on Communications.
[11] Ieee Microwave Theory,et al. Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems — Amendment for Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands , 2003 .
[12] Ali Emre Pusane,et al. A low-cost serial decoder architecture for low-density parity-check convolutional codes , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[13] Radford M. Neal,et al. Near Shannon limit performance of low density parity check codes , 1996 .
[14] Ramkrishna Swamy,et al. Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[15] David J. C. MacKay,et al. Good Error-Correcting Codes Based on Very Sparse Matrices , 1997, IEEE Trans. Inf. Theory.
[16] Gerhard Fettweis,et al. On the structured parallelism of decoders for LDPC convolutional codes - an algebraic description , 2009, 2009 IEEE International Symposium on Circuits and Systems.
[17] Gerhard Fettweis,et al. A dual-core programmable decoder for LDPC convolutional codes , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[18] S. Bates,et al. Design and Test of a 175-Mb/s, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder , 2007, IEEE Journal of Solid-State Circuits.
[19] J.P. Derutin,et al. Design of a Scalable Network of Communicating Soft Processors on FPGA , 2007, 2006 International Workshop on Computer Architecture for Machine Perception and Sensing.
[20] Norbert Wehn,et al. A 150Mbit/s 3GPP LTE Turbo code decoder , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[21] Naresh R. Shanbhag,et al. High-throughput LDPC decoders , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[22] Bruce F. Cockburn,et al. Jointly Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[23] Juntan Zhang,et al. Shuffled belief propagation decoding , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..
[24] Bruce F. Cockburn,et al. A Compact and Accurate Gaussian Variate Generator , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[25] Gerhard Fettweis,et al. Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[26] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[27] Qiuting Huang,et al. A 390Mb/s 3.57mm2 3GPP-LTE turbo decoder ASIC in 0.13µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).