Effects of annealing conditions on charge storage of Si nanocrystal memory devices obtained by low-energy ion beam synthesis
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N. Cherkashin | A. Claverie | M. Carrada | M. Ameen | D. Tsoukalas | P. Dimitrakis | G. Benassayag | P. Normand | C. Bonafos | A. Agarwal | E. Kapetanakis | K. Beltsios | D. Skarlatos | V. Soncini | C. Sohl
[1] J. Gautier,et al. Formation of 2-D arrays of semiconductor nanocrystals or semiconductor-rich nanolayers by very low-energy Si or Ge ion implantation in silicon oxide films , 2001 .
[2] Ya-Chin King,et al. Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/ , 2001 .
[3] Pascal Normand,et al. Charge storage and interface states effects in Si-nanocrystal memory obtained using low-energy Si+ implantation and annealing , 2000 .
[4] Sandip Tiwari,et al. Fast and long retention-time nano-crystal memory , 1996 .
[5] J. Berg,et al. Formation of 2‐D Arrays of Silicon Nanocrystals in Thin SiO2 Films by Very‐Low Energy Si + Ion Implantation , 1999 .