Challenges and directions for testing IC
暂无分享,去创建一个
[1] Nur A. Touba,et al. Test vector encoding using partial LFSR reseeding , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[2] Tony Ambler,et al. Economics of Built-in Self-Test , 2001, IEEE Des. Test Comput..
[3] T. H. Ning. A CMOS technology roadmap for the next fifteen years , 1995, 1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings.
[4] P. A. Gargini. The global route to future semiconductor technology , 2002 .
[5] Yervant Zorian,et al. Test of future system-on-chips , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[6] Dhiraj K. Pradhan,et al. GLFSR-a new test pattern generator for built-in-self-test , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] M. J. Morant,et al. Integrated Circuit Design and Technology , 1990 .
[8] David L. Landis,et al. Pseudo-exhaustive testing of sequential circuits , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.
[9] Arno Kunzmann,et al. Generation of deterministic test patterns by minimal basic test sets , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.
[10] Benoit Nadeau-Dostie,et al. A new procedure for weighted random built-in self-test , 1990, Proceedings. International Test Conference 1990.
[11] Michael H. Schulz,et al. Improved deterministic test pattern generation with applications to redundancy identification , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Edward J. McCluskey,et al. Pseudo-exhaustive test and segmentation: formal definitions and extended fault coverage results , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[13] Carl Sechen,et al. An efficient method for generating exhaustive test sets , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] Wojciech Maly,et al. Modeling the Economics of Testing: A DFT Perspective , 2002, IEEE Des. Test Comput..
[15] J. E. Brewer. A new and improved roadmap , 1998 .
[16] Edward J. McCluskey,et al. Circuits for pseudoexhaustive test pattern generation , 1986, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] Jacob Savir. On chip weighted random patterns , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).
[18] Q. Zhou,et al. Test support processors for enhanced testability of high performance circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[19] Melvin A. Breuer,et al. Novel test pattern generators for pseudo-exhaustive testing , 1993, Proceedings of IEEE International Test Conference - (ITC).
[20] Jacob Savir,et al. Built In Test for VLSI: Pseudorandom Techniques , 1987 .
[21] Bernard Courtois,et al. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers , 1995, IEEE Trans. Computers.
[22] Neil Kelly. BIST vs. ATE for testing system-on-a-chip , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[23] Jon Turino. Design for test and time to market-friends or foes , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[24] Edward J. McCluskey,et al. Circuits for Pseudo-Exhaustive Test Pattern Generation. , 1986 .
[25] J. Mucha,et al. Built-In Test for Complex Digital Integrated Circuits , 1979, Fifth European Solid State Circuits Conference - ESSCIRC 79.
[26] Nur A. Touba,et al. Pseudo-random pattern testing of bridging faults , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.
[27] Rochit Rajsuman. System-On-A-Chip: Design and Test , 2000 .
[28] Charles R. Kime,et al. MFBIST: a BIST method for random pattern resistant circuits , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[29] Edward J. McCluskey,et al. Design for Autonomous Test , 1981, IEEE Transactions on Computers.
[30] Stephen K. Sunter. BIST vs. ATE: need a different vehicle? , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[31] Parker,et al. Design for Testability—A Survey , 1982, IEEE Transactions on Computers.
[32] René David. Random Testing of Digital Circuits: Theory and Applications , 1998 .
[33] Stanley L. Hurst. VLSI Testing: Digital and mixed analogue/digital techniques , 1998 .
[34] Wayne M. Needham. Nanometer Technology Challenges for Test and Test Equipment , 1999, Computer.
[35] Arnaud Virazel,et al. Comparison between random and pseudo-random generation for BIST of delay, stuck-at and bridging faults , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).
[36] Chien-In Henry Chen,et al. Logic partitioning to pseudo-exhaustive test for BIST design , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[37] VISHWANI D. AGRAWAL. When to Use Random Testing , 1978, IEEE Transactions on Computers.
[38] W. J. Spencer,et al. National technology roadmaps: the U.S. semiconductor experience , 1995, Proceedings of 4th International Conference on Solid-State and IC Technology.
[39] G. E. Sobelman,et al. An efficient approach to pseudo-exhaustive test generation for BIST design , 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[40] Janak H. Patel,et al. New Techniques for Deterministic Test Pattern Generation , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).
[41] P. Gargini,et al. The International Technology Roadmap for Semiconductors (ITRS): "Past, present and future" , 2000, GaAs IC Symposium. IEEE Gallium Arsenide Integrated Circuits Symposium. 22nd Annual Technical Digest 2000. (Cat. No.00CH37084).
[42] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[43] D. M. Miller,et al. Exhaustive testing of stuck-open faults in CMOS combinational circuits , 1988 .
[44] S. Hellebrand,et al. An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[45] Yervant Zorian,et al. 2001 Technology Roadmap for Semiconductors , 2002, Computer.
[46] Wen-Ben Jone,et al. On partitioning for pseudo exhaustive testing of VLSI circuits , 1988, 1988., IEEE International Symposium on Circuits and Systems.
[47] B. Koenemann. LFSR-coded test patterns for scan designs , 1991 .