Study and development of an efficient RC-in-RC-out MOR method

This paper outlines the study and development of an efficient RC-in-RC-out model-order reduction (MOR) method suitable for reduction of very large sized RC circuits or the RC circuit parts of a non-RC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements. This benefit translates to a typical 10-100 times faster simulation with only a minimal error. The performance of the MOR method is evaluated with simulations and compared with other MOR algorithms.

[1]  A. Yang,et al.  Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations , 1996, 33rd Design Automation Conference Proceedings, 1996.

[2]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluator , 1991, 28th ACM/IEEE Design Automation Conference.

[3]  Janne Roos,et al.  Using METIS and hMETIS Algorithms in Circuit Partitioning , 2006 .

[4]  Bernard N. Sheehan,et al.  TICER: Realizable reduction of extracted RC circuits , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[5]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluation using AWE , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Chung-Kuan Cheng,et al.  Two-Stage Newton-Raphson Method for Transistor-Level Simulation , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[8]  Haifang Liao,et al.  Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[9]  George Karypis,et al.  A Software Package for Partitioning Unstructured Graphs , Partitioning Meshes , and Computing Fill-Reducing Orderings of Sparse Matrices Version 5 . 0 , 1998 .