BATCH APPLICATIONS OF DIGITAL BPM PROCESSORS FROM THE SINAP

During the past several years a digital BPM (DBPM) processor has been developed at the SINAP. After continuous development and optimization, the processor has been finalized and has come to batch application on the signal processing of cavity BPMs and stripline BPMs at the Dalian Coherent Light Source (DCLS) and the Shanghai Soft X-ray FEL (SXFEL). Tests have been done to evaluate the performances, such as the noise level, the SNR and the cross talk. The system resolution of the cavity and stripline BPMs can achieve 1um and 10um respectively. The test results on the Shanghai Deep-Ultra-Violet (SDUV) and the DCLS will be introduced. INTRODUCTION A prototype of the DBPM has been developed successfully at the SINAP during the past few years [1~5]. Some tests and applications have been carried out at the Shanghai Synchrotron Radiation Facility (SSRF)[6]. Since 2015, two FEL facilities, DCLS and SXFEL, have been under constructions. Dozens of stripline BPMs and cavity BPMs are planted along the LINAC accelerators and the undulators. To handle the BPM data acquisitions and the position calculations, a new in-house BPM processor has been designed. The main system structure of the previous DBPM has been kept for the new design, and some optimizations and modifications are implemented aiming at the application on FEL. Figure 1 is an overview of the system structure. It consists of 4 input RF signal conditioning blocks, 4 analogue to digital converters (ADC), a digital signal processing module, and a CPU running control system. Figure 1: DBPM processor architecture. HARDWARE DESIGN The processor includs four input channels, and it mainly consists of three boards: a carrier board implementing the RF conditioning and digitizer with ADCs, a mother board holds FPGA and other peripheral components and interfaces, and an ARM board conducting system control (as shown in Figure 2). Figure 2: Hardware diagram.