Safe Design Method of Embedded Control Systems based on COTS

In this paper, we propose an approach based on formal verification and discrete controller synthesis that are combined within a component-based design method. Formal verification finds design errors and provides counterexamples while the Discrete Controller Synthesis technique attempts to enforce previously verified specifications which do not hold. It automatically produces control code, which is correct by construction with respect to the specification to enforce. This approach is presented and illustrated on a train controller subsystem.

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