Distributed Instruction Set Computer Architecture
暂无分享,去创建一个
[1] James E. Smith,et al. Instruction Issue Logic in Pipelined Supercomputers , 1984, IEEE Trans. Computers.
[2] Joseph A. Fisher,et al. Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.
[3] Yale N. Patt,et al. HPS, a new microarchitecture: rationale and introduction , 1985, MICRO 18.
[4] Jack B. Dennis,et al. Data Flow Supercomputers , 1980, Computer.
[5] Chuan-lin Wu,et al. I-NET mechanism for issuing multiple instructions , 1988, Proceedings. SUPERCOMPUTING '88.
[6] Kattamuri Ekanadham,et al. Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution , 1987, IEEE Transactions on Computers.
[7] Michael J. Flynn,et al. Detection and Parallel Execution of Independent Instructions , 1970, IEEE Transactions on Computers.
[8] Alfred V. Aho,et al. Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.
[9] JOHN L. HENNESSY,et al. VLSI Processor Architecture , 1984, IEEE Transactions on Computers.
[10] David A. Padua,et al. A Second Opinion on Data Flow Machines and Languages , 1982, Computer.
[11] George Radin. The 801 Minicomputer , 1983, IBM J. Res. Dev..
[12] Edward M. Riseman,et al. Percolation of Code to Enhance Parallel Dispatching and Execution , 1972, IEEE Transactions on Computers.
[13] Gerry Kane,et al. MIPS R2000 RISC architecture , 1987 .
[14] Robert A. Iannucci. Toward a dataflow/von Neumann hybrid architecture , 1988, ISCA '88.
[15] Hwa C. Torng,et al. An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors , 1986, IEEE Transactions on Computers.
[16] C. V. Ramamoorthy,et al. Pipeline Architecture , 1977, CSUR.
[17] H. C. Torng. Introduction to the Special Issue on Supercomputing , 1987 .
[18] J. E. Thornton. Design of a Computer: The Control Data 6600 , 1970 .
[19] Robert P. Colwell,et al. A VLIW architecture for a trace scheduling compiler , 1987, ASPLOS 1987.
[20] Arvind,et al. A critique of multiprocessing von Neumann style , 1983, ISCA '83.
[21] B. Ramakrishna Rau,et al. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing , 1981, MICRO 14.
[22] David A. Patterson,et al. Reduced instruction set computers , 1985, CACM.
[23] R. M. Tomasulo,et al. An efficient algorithm for exploiting multiple arithmetic units , 1995 .