Generation Dependence of Retention Characteristics in Extremely Scaled NAND Flash Memory
暂无分享,去创建一个
Hyungcheol Shin | Yuchul Hwang | Dong Hua Li | Duckseoung Kang | Shinhyung Kim | Dong-Seok Bae | Hyungcheol Shin | Yuchul Hwang | Kyunghwan Lee | Seongjun Seo | D. Li | D. Kang | Shinhyung Kim | Ji-Seok Lee | Dong-seok Bae | Kyunghwan Lee | Seongjun Seo | Ji-Seok Lee
[1] Kinam Kim,et al. The new program/erase cycling degradation mechanism of NAND flash memory devices , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).
[2] Karl Hess,et al. On the mechanism of interface trap generation under nonuniform channel-hot-electron stress and uniform carrier-injection stress in metal–oxide–semiconductor field-effect transistors , 2001 .
[3] Myounggon Kang,et al. Activation Energies $(E_{a})$ of Failure Mechanisms in Advanced NAND Flash Cells for Different Generations and Cycling , 2013, IEEE Transactions on Electron Devices.
[4] Byung-Gook Park,et al. The Compact Modeling of Channel Potential in Sub-30-nm NAND Flash Cell String , 2012, IEEE Electron Device Letters.
[5] Myounggon Kang,et al. Analysis of Failure Mechanisms and Extraction of Activation Energies $(E_{a})$ in 21-nm nand Flash Cells , 2013, IEEE Electron Device Letters.
[6] Myounggon Kang,et al. An Accurate Compact Model Considering Direct-Channel Interference of Adjacent Cells in Sub-30-nm nand Flash Technologies , 2012, IEEE Electron Device Letters.
[7] A. Visconti,et al. Threshold-Voltage Instability Due to Damage Recovery in Nanoscale NAND Flash Memories , 2011, IEEE Transactions on Electron Devices.
[8] Jelke Dijkstra,et al. Tail bit implications in advanced 2 transistors-flash memory device reliability , 2001 .
[9] Kinam Kim,et al. Degradation of tunnel oxide by FN current stress and its effects on data retention characteristics of 90 nm NAND flash memory cells , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[10] Krishna Parat,et al. 25nm 64Gb MLC NAND technology and scaling challenges invited paper , 2010, 2010 International Electron Devices Meeting.
[11] M.A. Alam,et al. Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs , 2004, IEEE Transactions on Electron Devices.
[12] Min-su Kim,et al. A High Performance Co-design of 26 nm 64 Gb MLC NAND Flash Memory using the Dedicated NAND Flash Controller , 2011 .