A heuristic for thermal-safe SoC test scheduling

High temperature has become a technological barrier to the testing of high performance systems-on-chip, especially when deep submicron technologies are employed. In order to reduce test time while keeping the temperature of the cores under test within a safe range, thermal-aware test scheduling techniques are required. In this paper, we address the test time minimization problem as how to generate the shortest test schedule such that the temperature limits of individual cores and the limit on the test-bus bandwidth are satisfied. In order to avoid overheating during the test, we partition test sets into shorter test subsequences and add cooling periods in between, such that continuously applying a test sub-sequence will not drive the core temperature going beyond the limit. Further more, based on the test partitioning scheme, we interleave the test sub-sequences from different test sets in such a manner that a cooling period reserved for one core is utilized for the test transportation and application of another core. We have proposed a heuristic to minimize the test application time by exploring alternative test partitioning and interleaving schemes with variable length of test sub-sequences and cooling periods. Experimental results have shown the efficiency of the proposed heuristic.

[1]  Kevin Skadron,et al.  HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Prab Varma,et al.  A structured test re-use methodology for core-based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[3]  Petru Eles,et al.  Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving , 2008, J. Electron. Test..

[4]  Erik Jan Marinissen,et al.  Control-aware test architecture design for modular SOC testing , 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

[5]  Stephen H. Gunther,et al.  Managing the Impact of Increasing Microprocessor Power Consumption , 2001 .

[6]  Krishnendu Chakrabarty,et al.  Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Harald Dyckhoff,et al.  A typology of cutting and packing problems , 1990 .

[8]  Alfred L. Crouch,et al.  Optimization trade-offs for vector volume and test power , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[9]  Erik G. Larsson,et al.  An Integrated Framework for the Design and Optimization of SOC Test Solutions , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[10]  Nilanjan Mukherjee,et al.  Resource allocation and test scheduling for concurrent test of core-based SOC design , 2001, Proceedings 10th Asian Test Symposium.

[11]  Joe Marks,et al.  Exhaustive approaches to 2D rectangular perfect packings , 2004, Inf. Process. Lett..

[12]  Vishwani D. Agrawal,et al.  Scheduling tests for VLSI systems under power constraints , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[13]  E.J. Marinissen,et al.  Scan chain design for test time reduction in core-based ICs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[14]  Kevin Skadron,et al.  Temperature-aware microarchitecture: Modeling and implementation , 2004, TACO.

[15]  Erik Jan Marinissen,et al.  Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip , 2003, IEEE Trans. Computers.

[16]  Krishnendu Chakrabarty,et al.  Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling , 2006, 2006 IEEE International Test Conference.

[17]  Kevin Skadron,et al.  Compact thermal modeling for temperature-aware design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[18]  Chunsheng Liu,et al.  Thermal-aware test scheduling and hot spot temperature minimization for core-based systems , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[19]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[20]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[21]  Yervant Zorian,et al.  Testing Embedded-Core-Based System Chips , 1999, Computer.

[22]  Ronald L. Rivest,et al.  Orthogonal Packings in Two Dimensions , 1980, SIAM J. Comput..

[23]  John P. Hayes,et al.  Testing ICs: Getting to the Core of the Problem , 1996, Computer.

[24]  Petru Eles,et al.  Power Constrained and Defect-Probability Driven SoC Test Scheduling with Test Set Partitioning , 2006, Proceedings of the Design Automation & Test in Europe Conference.