A Test Circuit for Statistical Evaluation of $p-n$ Junction Leakage Current and its Noise

We develop a test circuit to evaluate statistical distributions of p-n junction leakage currents for numerous samples in a very short time (0.1-10 fA, 28672 n+-p diodes in 0.77s). This test circuit is based on a complementary metal-oxide-semiconductor active pixel image sensor, which contains a current-to-voltage conversion function by a capacitor and amplifiers of voltage signals in each pixel. The test structure can be easily designed because of a small number of mask layer requirements (at least one poly-Si, one metal interconnect layer). Its simplicity has considerable benefits, such as an easy fabrication for the evaluation of various processes technologies without exceptional cares. We demonstrate that two normal distributions exist in the steady-state (time averaging) Ileak distributions, which have differing temperature dependencies. A distribution of the activation energy extracted from temperature dependence of Ileak is also revealed experimentally. Dynamic fluctuation of Ileak is confirmed to be measured, due to the execute pseudoparallel sampling among whole samples over a long recording time.

[1]  K. Ohyu,et al.  Quantitative identification for the physical origin of variable retention time: A vacancy-oxygen complex defect model , 2006, 2006 International Electron Devices Meeting.

[2]  Eric R. Fossum,et al.  CMOS image sensors: electronic camera on a chip , 1995, Proceedings of International Electron Devices Meeting.

[3]  Jeong-Mo Hwang,et al.  Accurate extraction of reverse leakage current components of shallow silicided p/sup +/-n junction for quarter- and sub-quarter-micron MOSFET's , 1998 .

[4]  A. Hiraiwa,et al.  Statistical modeling of dynamic random access memory data retention characteristics , 1996 .

[5]  Gwan-Hyeob Koh,et al.  Anomalous junction leakage current induced by STI dislocations and its impact on dynamic random access memory devices , 1999 .

[6]  Tadahiro Ohmi,et al.  Stress-induced leakage current and random telegraph signal , 2009 .

[7]  Y. Mori,et al.  The origin of variable retention time in DRAM , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[8]  S. S. Park,et al.  The analysis of dark signals in the CMOS APS imagers from the characterization of test structures , 2004 .

[9]  D. Yaney,et al.  A meta-stable leakage phenomenon in DRAM charge storage —Variable hold time , 1987, 1987 International Electron Devices Meeting.

[10]  Tadahiro Ohmi,et al.  A test structure for statistical evaluation of pn junction leakage current based on CMOS image sensor technology , 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).

[11]  Rita Rooyackers,et al.  Shallow trench isolation dimensions effects on leakage current and doping concentration of advanced p–n junction diodes , 2004 .

[12]  J. Vallerga,et al.  Counting of deep-level traps using a charge-coupled device , 1987, IEEE Transactions on Electron Devices.

[13]  Tadahiro Ohmi,et al.  Asymmetry of RTS characteristics along source-drain direction and statistical analysis of process-induced RTS , 2009, 2009 IEEE International Reliability Physics Symposium.

[14]  S. Sugawa,et al.  Statistical evaluation for anomalous SILC of tunnel oxide using integrated array TEG , 2008, 2008 IEEE International Reliability Physics Symposium.

[15]  T.Y. Chan,et al.  The impact of gate-induced drain leakage current on MOSFET scaling , 1987, 1987 International Electron Devices Meeting.

[16]  A. Teramoto,et al.  Accurate Time Constant of Random Telegraph Signal Extracted by a Sufficient Long Time Measurement in Very Large-Scale Array TEG , 2009, 2009 IEEE International Conference on Microelectronic Test Structures.

[17]  T. Hamamoto,et al.  On the retention time distribution of dynamic random access memory (DRAM) , 1998 .

[18]  J. W. Park,et al.  DRAM variable retention time , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[19]  Chenming Hu,et al.  Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[20]  Tadahiro Ohmi,et al.  New Statistical Evaluation Method for the Variation of Metal–Oxide–Semiconductor Field-Effect Transistors , 2007 .

[21]  Hyungcheol Shin,et al.  RTS-like fluctuation in Gate Induced Drain Leakage current of Saddle-Fin type DRAM cell transistor , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[22]  Hyuck In Kwon,et al.  The analysis of dark signals in the CMOS APS imagers from the characterization of test structures , 2004, IEEE Transactions on Electron Devices.

[23]  A. Theuwissen,et al.  Leakage current modeling of test structures for characterization of dark current in CMOS image sensors , 2003 .

[24]  K. Yamaguchi.  Theoretical study of deep-trap-assisted anomalous currents in worst-bit cells of dynamic random-access memories (DRAM's) , 2000 .

[25]  A. Teramoto,et al.  A Test Structure for Statistical Evaluation of Characteristics Variability in a Very Large Number of MOSFETs , 2009, 2009 IEEE International Conference on Microelectronic Test Structures.

[26]  Tadahiro Ohmi,et al.  Anomalous Random Telegraph Signal Extractions from a Very Large Number of n-Metal Oxide Semiconductor Field-Effect Transistors Using Test Element Groups with 0.47 Hz–3.0 MHz Sampling Frequency , 2009 .

[27]  S. Sugawa,et al.  Random Telegraph Signal Statistical Analysis using a Very Large-scale Array TEG with 1M MOSFETs , 2007, 2007 IEEE Symposium on VLSI Technology.