A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
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Giacomo Indiveri | Ning Qiao | Saber Moradi | Fabio Stefanini | F. Stefanini | G. Indiveri | Ning Qiao | S. Moradi
[1] Bernabé Linares-Barranco,et al. Feedforward Categorization on AER Motion Events Using Cortex-Like Features in a Spiking Neural Network , 2015, IEEE Transactions on Neural Networks and Learning Systems.
[2] R. Douglas,et al. A Quantitative Map of the Circuit of Cat Primary Visual Cortex , 2004, The Journal of Neuroscience.
[3] Andrew S. Cassidy,et al. Convolutional networks for fast, energy-efficient neuromorphic computing , 2016, Proceedings of the National Academy of Sciences.
[4] Chiara Bartolozzi,et al. Neuromorphic Electronic Circuits for Building Autonomous Cognitive Systems , 2014, Proceedings of the IEEE.
[5] Mingoo Seok,et al. Energy-Efficient Neuromorphic Classifiers , 2016, Neural Computation.
[6] Cyrille C. Girardin,et al. Embedding of Cortical Representations by the Superficial Patch System , 2011, Cerebral cortex.
[7] Giacomo Indiveri,et al. A VLSI network of spiking neurons with an asynchronous static random access memory , 2011, 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS).
[8] John W. Backus,et al. Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs , 1978, CACM.
[9] Giacomo Indiveri,et al. An Event-Based Neural Network Architecture With an Asynchronous Programmable Synaptic Memory , 2014, IEEE Transactions on Biomedical Circuits and Systems.
[10] Bernabé Linares-Barranco,et al. Mapping from Frame-Driven to Frame-Free Event-Driven Vision Systems by Low-Rate Rate Coding and Coincidence Processing--Application to Feedforward ConvNets , 2013, IEEE Transactions on Pattern Analysis and Machine Intelligence.
[11] Wulfram Gerstner,et al. Firing patterns in the adaptive exponential integrate-and-fire model , 2008, Biological Cybernetics.
[12] Chiara Bartolozzi,et al. Synaptic Dynamics in Analog VLSI , 2007, Neural Computation.
[13] Kwabena Boahen,et al. Point-to-point connectivity between neuromorphic chips using address events , 2000 .
[14] Guigang Zhang,et al. Deep Learning , 2016, Int. J. Semantic Comput..
[15] C. A. R. Hoare,et al. Communicating sequential processes , 1978, CACM.
[16] Hisashi Shima,et al. Resistive Random Access Memory (ReRAM) Based on Metal Oxides , 2010, Proceedings of the IEEE.
[17] Francesco Galluppi,et al. A forecast-based STDP rule suitable for neuromorphic implementation , 2012, Neural Networks.
[18] Yong Liu,et al. Specifications of Nanoscale Devices and Circuits for Neuromorphic Computational Systems , 2013, IEEE Transactions on Electron Devices.
[19] Alain J. Martin,et al. Asynchronous Techniques for System-on-Chip Design , 2006, Proceedings of the IEEE.
[20] Garrick Orchard,et al. HOTS: A Hierarchy of Event-Based Time-Surfaces for Pattern Recognition , 2017, IEEE Transactions on Pattern Analysis and Machine Intelligence.
[21] K. Pagiamtzis,et al. Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.
[22] Deepak Khosla,et al. Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition , 2014, International Journal of Computer Vision.
[23] Rodrigo Alvarez-Icaza,et al. Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations , 2014, Proceedings of the IEEE.
[24] Rajit Manohar. Reconfigurable Asynchronous Logic , 2006, IEEE Custom Integrated Circuits Conference 2006.
[25] Matthew Cook,et al. Fast-classifying, high-accuracy spiking deep networks through weight and threshold balancing , 2015, 2015 International Joint Conference on Neural Networks (IJCNN).
[26] Alain J. Martin. The limitations to delay-insensitivity in asynchronous circuits , 1990 .
[27] Stephan Henker,et al. A 32 GBit/s communication SoC for a waferscale neuromorphic system , 2012, Integr..
[28] Eugene M. Izhikevich,et al. Dynamical Systems in Neuroscience: The Geometry of Excitability and Bursting , 2006 .
[29] Tobi Delbrück,et al. 32-bit Configurable bias current generator with sub-off-current capability , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[30] Peter Dayan,et al. Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems , 2001 .
[31] Giacomo Indiveri,et al. Memory and Information Processing in Neuromorphic Systems , 2015, Proceedings of the IEEE.
[32] Bernabé Linares-Barranco,et al. Poker-DVS and MNIST-DVS. Their History, How They Were Made, and Other Details , 2015, Front. Neurosci..
[33] Andrew S. Cassidy,et al. A million spiking-neuron integrated circuit with a scalable communication network and interface , 2014, Science.
[34] R. Waser,et al. Resistive Switching: From Fundamentals of Nanoionic Redox Processes to Memristive Device Applications , 2016 .
[35] R. Douglas,et al. Recurrent neuronal circuits in the neocortex , 2007, Current Biology.
[36] Paul E. Hasler,et al. Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit , 2013, Neural Networks.
[37] A. Litwin-Kumar,et al. Formation and maintenance of neuronal assemblies through synaptic plasticity , 2014, Nature Communications.
[38] Giacomo Indiveri,et al. Scaling mixed-signal neuromorphic processors to 28 nm FD-SOI technologies , 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).
[39] Bernabé Linares-Barranco,et al. An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors , 2012, IEEE Journal of Solid-State Circuits.
[40] Giacomo Indiveri,et al. A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses , 2015, Front. Neurosci..
[41] Janet Wiles,et al. Spike Event Based Learning in Neural Networks , 2015, ArXiv.
[42] Gert Cauwenberghs,et al. Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems , 2017, IEEE Transactions on Neural Networks and Learning Systems.
[43] Steve B. Furber,et al. The SpiNNaker Project , 2014, Proceedings of the IEEE.
[44] Nitish V. Thakor,et al. HFirst: A Temporal Approach to Object Recognition , 2015, IEEE Transactions on Pattern Analysis and Machine Intelligence.
[45] Bernabé Linares-Barranco,et al. Multicasting Mesh AER: A Scalable Assembly Approach for Reconfigurable Neuromorphic Structured AER Systems. Application to ConvNets , 2013, IEEE Transactions on Biomedical Circuits and Systems.
[46] Henry Kennedy,et al. The importance of being hierarchical , 2013, Current Opinion in Neurobiology.
[47] Giacomo Indiveri,et al. A memory-efficient routing method for large-scale spiking neural networks , 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).