Increasing the instruction fetch rate via multiple branch prediction and a branch address cache

"Increasing the Instruction Fetch Rate viaMultiple Branch Prediction and a Branch Address Cache" was the first paper to propose a highly accurate hardware mechanism for predicting and fetching multiple non-contiguous basic blocks using leading-edge aggressive branch predictors of the time. Prior to this paper, the methods to increase fetch bandwidth relied on software and compiler mechanisms to increase the size of the basic blocks themselves. The publication of our paper inspired an explosion of research to further improve the accuracy of multiple branch prediction, reduce complexity of fetching multiple basic blocks, or increase the fetch bandwidth in other ways. Our HPS research group defied conventional wisdom in a 1991 ISCA paper [1] that demonstrated instruction level parallelism (IPC) can be greater than two even for non-scientific workloads. This flew in the face of numerous "proofs" at the time. We showed that there was enough parallelism for an aggressive superscalar out-of-order execution engine to exploit to dramatically improve performance, provided that the penalties caused by incorrect branch predictions, cache misses, and TLB misses could be improved.