A 5-Gb/s CMOS Optical Receiver with Regulated-Cascode Input Stage for 1.2V Supply

This paper presents a 5-Gb/s optical receiver circuit realized in a CMOS technologies for the applications of high-speed digital interface. Exploiting modified RGC input stage at the front-end transimpedance amplifier, interleaving active feedback and source degeneration techniques at the limiting amplifier, the proposed optical receiver chip demonstrates the measured results of transimpedance gain, 4.7-GHz bandwidth, and differential output voltage swings up to the data rate of 5-Gb/s. Also, the chip dissipates 66mW in total from a single 1.2-V supply, and occupies the area of .