Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis

Stringent quality requirements for integrated, heterogeneous systems have led designers and test engineers to mandate large sets of tests to be applied to these systems, which, in turn, have resulted in increased test cost. However, many of these tests are unnecessary (i.e., redundant), since their outcomes can be reliably predicted using results from other applied tests. A methodology for identifying the redundant tests of an integrated, heterogeneous system that has only binary pass-fail test data is described. This methodology uses decision trees, Boolean minimization, and satisfiability as core components. Feasibility is empirically demonstrated using test data from two commercially fabricated systems, namely, a high-speed serializer/deserializer (HSS) and a phase-locked loop (PLL). Our analysis of test data from > 38,000 HSS and > 22,000 PLL circuits show that 14 out of 40 HSS tests and 11 out of 36 PLL tests are redundant.

[1]  Yiorgos Makris,et al.  Non-RF to RF Test Correlation Using Learning Machines: A Case Study , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[2]  Yiorgos Makris,et al.  Nonlinear decision boundaries for testing analog circuits , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  R. D. Blanton,et al.  Statistical Test Compaction Using Binary Decision Trees , 2006, IEEE Design & Test of Computers.

[4]  Kenneth M. Butler,et al.  Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Lior Rokach,et al.  Top-down induction of decision trees classifiers - a survey , 2005, IEEE Transactions on Systems, Man, and Cybernetics, Part C (Applications and Reviews).

[6]  R. D. Blanton,et al.  Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Jay B. Brockman,et al.  Predictive subset testing: optimizing IC parametric performance testing for quality, cost, and yield , 1989 .

[8]  Hai Zhou,et al.  Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems , 2010 .

[9]  G. S. Tseitin.  On the Complexity of Derivation in Propositional Calculus , 1983 .

[10]  R. D. Blanton,et al.  Maintaining Accuracy of Test Compaction through Adaptive Re-learning , 2009, 2009 27th IEEE VLSI Test Symposium.

[11]  Alberto L. Sangiovanni-Vincentelli,et al.  Minimizing production test time to detect faults in analog circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Magdy S. Abadir,et al.  Statistical analysis and optimization of parametric delay test , 2007, 2007 IEEE International Test Conference.

[13]  Abhijit Chatterjee,et al.  Alternate electrical tests for extracting mechanical parameters of MEMS accelerometer sensors , 2006, 24th IEEE VLSI Test Symposium.

[14]  Abhijit Chatterjee,et al.  Test generation for accurate prediction of analog specifications , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[15]  Patrick D.T. O'Connor.  The Economics of Automatic Testing , 1983 .

[16]  R. D. Blanton,et al.  Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[17]  Hui Xiong,et al.  The minimum consistent subset cover problem and its applications in data mining , 2007, KDD '07.

[18]  Ronald S. Gyurcsik,et al.  Optimal ordering of analog integrated circuit tests to minimize test time , 1991, 28th ACM/IEEE Design Automation Conference.