Overcoming scaling barriers through design technology CoOptimization
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Lei Yuan | Jongwook Kye | Guillaume Bouche | Lars Liebmann | Xuelian Zhu | Jia Zeng | J. Kye | Lei Yuan | Xuelian Zhu | G. Bouche | L. Liebmann | J. Zeng
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[2] Diederik Verkest,et al. Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs , 2016, SPIE Advanced Lithography.