Analysis of the structural efficiency of digital signal processing algorithms and their implementation on parallel processing architectures

A methodology for the analysis of the structure of a given digital signal processing algorithm is presented. The task precedence relationships within a scheduling cycle are derived for scheduling cycles that contain one and two basic cycles, which is sufficient to derive the precedence relationships for scheduling cycles that contain an arbitrary number of basic cycles. The schedules considered are deterministic and non-preemptive for multiprocessor parallel environments with a variable number of processing elements. The complexity algorithm is analyzed, and its application to the development of digital signal processing software for systems which impose an execution speed constraint is discussed.<<ETX>>