An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers

An experimental 4 K word by 256 b CMOS synchronous SRAM employing read/write shared sense amplifiers and self-timed pulsed word-lines is described. The read/write shared sense amplifier allows the RAM to have 256 I/Os and the self-timed pulsed word-line scheme reduces power consumption. Fully differential I/O buses, laid out in fourth metal over the memory cell arrays, use a 0.3 V differential swing. The SRAM is fabricated in a 0.35 /spl mu/m four-layer metal CMOS process employing a 6-T SRAM cell measuring 5.2 /spl mu/m/spl times/6.6 /spl mu/m. The die measures 13.22 mm/spl times/4.80 mm. The SRAM operates at 295 MHz with a 3.3 V supply, achieving a bandwidth of 9.44 Gbyte/s.