On the Generation of Weights for Weighted Pseudo Random Testing

A method for weighted pseudo-random test generation based on a deterministic test se1 was described in [7], that uses only [0,0.5,1] weights. Two extensions of this method are described here. The first extension is aimed at reducing the hardware complexity of weighted random test pattern generators by assigning the 0.5 weights to a fixed set of inputs. The second extension involves the application of the method to two-pattern tests. Experimental results regarding both extensions are provided.

[1]  Irith Pomeranz,et al.  3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set , 1992, The Fifth International Conference on VLSI Design.

[2]  S. Reddy,et al.  COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[3]  Sheldon B. Akers,et al.  Test set embedding in a built-in self-test environment , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[4]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Eric Lindbloom,et al.  The Weighted Random Test-Pattern Generator , 1975, IEEE Transactions on Computers.

[6]  Janusz Rajski,et al.  Cube-Contained Random Patterns and their Application to the Complete Testing of Synthesized Multi-le , 1991, 1991, Proceedings. International Test Conference.

[7]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[8]  Janusz Rajski,et al.  Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits , 1991 .

[9]  Hans-Joachim Wunderlich,et al.  Multiple distributions for biased random test patterns , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[10]  Irith Pomeranz,et al.  COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[11]  Benoit Nadeau-Dostie,et al.  A new procedure for weighted random built-in self-test , 1990, Proceedings. International Test Conference 1990.

[12]  John A. Waicukauski,et al.  Transition Fault Simulation by Parallel Pattern Single Fault Propagation , 1986, International Test Conference.