A low complexity approach for fault detection in C-testable orthogonal VLSI arrays

Abstract This paper presents an extension to existing approaches for fault detection and C-testability of orthogonal iterative arrays. C-testability is given by a testing process whose complexity is independent of the dimensions of the arrays and the erroneous states of the cells. The state transition table of a basic cell is analyzed. Five new states are added to it. These states are used to internally reproduce the test input and propagate the faulty state to the output pins of a chip. The testing process is exhaustively analyzed. The characteristics of the additional states are presented. Complexity of the testing process (number of test vectors) is discussed. It is proved that even though the number of additinal states in the proposed approach is greater than previous approaches (five states compared with four), the required number of test vectors is considerably reduced. Illustrative examples are given. An approach to implement the proposed C-testability approach into logic design is also presented. Complexity of this implementation is analyzed. A conjecture about a possible relation between the number of additional states and the complexity of the testing process is postulated.

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