Galatea neural VLSI architectures: Communication and control considerations

Abstract The solution of real applications with neural computation generally involves a considerable number of neurons. The large number of units makes the one to one correspondence between neurons and physical processors unacceptable. In this paper we describe ways to map an arbitrary number of neurons into physical processors. In particular, we focus on the four digital neural architectures envisaged in the ESPRIT II Galatea Project (Siemens, Philips, INPG, and UCL VLSI architectures), explaining how their architectural design influences the communication and control issues.

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