Building Block Layout by Parallel Simulated

The Building Block Layout (BBL) becomes a more and more important approach for VLSI physical design. In this paper, based on the BBL floorplan problem, we discussed several parallel Simulated Annealing (SA) strategies. Two parallel simulated annealing algorithms are realized, using sequence- pair (SP) as the representation. Parallel algorithm can be used either to speed up a problem or to achieve a higher accuracy of solutias to a problem. In this work we are interested in the latter goal. The results from the experiment indicate that the proposed method parallelizes the routine of state transitions in SA to obtain better states efficiently.