Toward Reliable Multi-Level Operation in RRAM Arrays: Improving Post-Algorithm Stability and Assessing Endurance/Data Retention

Achieving a reliable multi-level operation in resistive random access memory (RRAM) arrays is currently a challenging task due to several threats like the post-algorithm instability occurring after the levels placement, the limited endurance, and the poor data retention capabilities at high temperature. In this paper, we introduced a multi-level variation of the state-of-the-art incremental step pulse with verify algorithm (M-ISPVA) to improve the stability of the low resistive state levels. This algorithm introduces for the first time the proper combination of current compliance control and program/verify paradigms. The validation of the algorithm for forming and set operations has been performed on 4-kbit RRAM arrays. In addition, we assessed the endurance and the high temperature multi-level retention capabilities after the algorithm application proving a 1 k switching cycles stability and a ten years retention target with temperatures below 100 °C.

[1]  Shimeng Yu,et al.  An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation , 2011, IEEE Transactions on Electron Devices.

[2]  G. Cibrario,et al.  Fundamental variability limits of filament-based RRAM , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[3]  Piero Olivo,et al.  Electrical characterization and modeling of pulse-based forming techniques in RRAM arrays , 2016 .

[4]  Piero Olivo,et al.  Implications of the Incremental Pulse and Verify Algorithm on the Forming and Switching Distributions in RERAM Arrays , 2016, IEEE Transactions on Device and Materials Reliability.

[5]  Hyunsang Hwang,et al.  Investigation of State Stability of Low-Resistance State in Resistive Memory , 2010, IEEE Electron Device Letters.

[6]  D. Gilmer,et al.  Metal oxide resistive memory switching mechanism based on conductive filament properties , 2011 .

[7]  D. Ielmini,et al.  Size-Dependent Retention Time in NiO-Based Resistive-Switching Memories , 2010, IEEE Electron Device Letters.

[8]  Kunji Chen,et al.  Characteristics of multilevel storage and switching dynamics in resistive switching cell of Al2O3/HfO2/Al2O3 sandwich structure , 2018 .

[9]  Seonghyun Kim,et al.  New Set/Reset Scheme for Excellent Uniformity in Bipolar Resistive Memory , 2011, IEEE Electron Device Letters.

[10]  Shimeng Yu,et al.  Metal–Oxide RRAM , 2012, Proceedings of the IEEE.

[11]  Byung Joon Choi,et al.  Resistive switching mechanism of TiO2 thin films grown by atomic-layer deposition , 2005 .

[12]  C. Zambelli,et al.  Multilevel HfO2-based RRAM devices for low-power neuromorphic networks , 2019, APL Materials.

[13]  Spyros Stathopoulos,et al.  Multibit memory operation of metal-oxide bi-layer memristors , 2017, Scientific Reports.

[14]  D. Ielmini,et al.  Modeling the Universal Set/Reset Characteristics of Bipolar RRAM by Field- and Temperature-Driven Filament Growth , 2011, IEEE Transactions on Electron Devices.

[15]  E. Vianello,et al.  On the Origin of Low-Resistance State Retention Failure in HfO2-Based RRAM and Impact of Doping/Alloying , 2015, IEEE Transactions on Electron Devices.

[16]  Piero Olivo,et al.  Characterization of the interface-driven 1st Reset operation in HfO2-based 1T1R RRAM devices , 2019, Solid-State Electronics.

[17]  Shimeng Yu,et al.  Investigation of statistical retention of filamentary analog RRAM for neuromophic computing , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[18]  E. Vianello,et al.  HfO2-Based RRAM: Electrode Effects, Ti/HfO2 Interface, Charge Injection, and Oxygen (O) Defects Diffusion Through Experiment and Ab Initio Calculations , 2016, IEEE Transactions on Electron Devices.

[19]  Hyunsang Hwang,et al.  Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaOx-Based RRAM by Stack Engineering , 2015, IEEE Electron Device Letters.

[20]  C. Cagli,et al.  Role of Ti and Pt electrodes on resistance switching variability of HfO2-based Resistive Random Access Memory , 2013 .

[21]  A. Cabrini,et al.  Intrinsic program instability in HfO2 RRAM and consequences on program algorithms , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[22]  P. Olivo,et al.  Relationship among Current Fluctuations during Forming, Cell-To-Cell Variability and Reliability in RRAM Arrays , 2015, 2015 IEEE International Memory Workshop (IMW).

[23]  H.-S. Philip Wong,et al.  Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell , 2019, IEEE Transactions on Electron Devices.

[24]  Ming-Hsiu Lee,et al.  Multi-level 40nm WOX resistive memory with excellent reliability , 2011, 2011 International Electron Devices Meeting.

[25]  R. Degraeve,et al.  Tailoring switching and endurance / retention reliability characteristics of HfO2 / Hf RRAM with Ti, Al, Si dopants , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

[26]  P. Pavan,et al.  A Novel Program-Verify Algorithm for Multi-Bit Operation in HfO2 RRAM , 2015, IEEE Electron Device Letters.

[27]  Piero Olivo,et al.  Data retention investigation in Al:HfO2-based resistive random access memory arrays by using high-temperature accelerated tests , 2019, Journal of Vacuum Science & Technology B.

[28]  Sang Gil Lee,et al.  Four-Bits-Per-Cell Operation in an HfO2 -Based Resistive Switching Device. , 2017, Small.

[29]  W. J. Liu,et al.  Highly Uniform, Self-Compliance, and Forming-Free ALD $\hbox{HfO}_{2}$ -Based RRAM With Ge Doping , 2012, IEEE Transactions on Electron Devices.

[30]  C. Hu,et al.  Effect of Top Electrode Material on Resistive Switching Properties of $\hbox{ZrO}_{2}$ Film Memory Devices , 2007, IEEE Electron Device Letters.

[31]  Y. G. Wang,et al.  Resistive switching mechanisms relating to oxygen vacancies migration in both interfaces in Ti/HfOx/Pt memory devices , 2013 .

[32]  D. Gilmer,et al.  Controlling uniformity of RRAM characteristics through the forming process , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[33]  Shimeng Yu,et al.  On the Switching Parameter Variation of Metal Oxide RRAM—Part II: Model Corroboration and Device Design Strategy , 2012, IEEE Transactions on Electron Devices.

[34]  C. Zambelli,et al.  Reduction of the Cell-to-Cell Variability in Hf1-xAlxOy Based RRAM Arrays by Using Program Algorithms , 2017, IEEE Electron Device Letters.

[35]  Piero Olivo,et al.  Statistical analysis of resistive switching characteristics in ReRAM test arrays , 2014, 2014 International Conference on Microelectronic Test Structures (ICMTS).