A 4.2 mW 5.7-GHz frequency synthesizer with dynamic-logic (TSPC) frequency divider

This paper presents a Phase-Locked Loop (PLL) used as a frequency synthesizer for a radio-frequency (RF) transceiver for use in the 5.7 ISM band, which were designed in the UMC RF 0.18 µm CMOS process. The PLL produces a set of different 16 digitally programmable frequencies in the [5424; 5830 MHz] frequency range. The low-power operation is achieved with the use of dynamic logic in the feedback path. Simulations shown a total power consumption of 4.2 mW. Target applications are wireless sensors and microsystems applications that need RF transceivers for operation in the 5.7 GHz band.

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