Codem: software/hardware codesign for embedded multicore systems supporting hardware services
暂无分享,去创建一个
Nadia Nedjah | Chao Wang | Aili Wang | Xuehai Zhou | Xi Li
[1] Nadia Nedjah,et al. A Hardware/Software Co-Design versus Hardware-only Implementation of Modular Exponentiation Using the Sliding-Window Method , 2009, J. Circuits Syst. Comput..
[2] Scott Hauck,et al. The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[3] Jürgen Teich,et al. A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAs , 2009, FPGA '09.
[4] Christoforos E. Kozyrakis,et al. RAMP: Research Accelerator for Multiple Processors , 2007, IEEE Micro.
[5] Nadia Nedjah,et al. Migration selection of strategies for parallel genetic algorithms: implementation on networks on chips , 2010 .
[6] Kunle Olukotun,et al. The Future of Microprocessors , 2005, ACM Queue.
[7] Keith D. Underwood,et al. Scientific Application Demands on a Reconfigurable Functional Unit Interface , 2011, TRETS.
[8] Seth Copen Goldstein,et al. PipeRench: A Reconfigurable Architecture and Compiler , 2000, Computer.
[9] Scott Hauck,et al. Reconfigurable computing: a survey of systems and software , 2002, CSUR.
[10] Stamatis Vassiliadis,et al. The MOLEN processor prototype , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.
[11] Satnam Singh. Computing without processors , 2012, CODES+ISSS '12.
[12] David Tarditi,et al. Accelerator: using data parallelism to program GPUs for general-purpose uses , 2006, ASPLOS XII.
[13] Anant Agarwal,et al. Factored operating systems (fos): the case for a scalable operating system for multicores , 2009, OPSR.
[14] Ralph Wittig,et al. OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[15] Weijia Shang,et al. ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.
[16] M. V.C. da Silva,et al. Power-aware multi-objective evolutionary optimisation for application mapping on network-on-chip platforms , 2010 .
[17] Jürgen Becker,et al. Runtime adaptive multi-processor system-on-chip: RAMPSoC , 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.
[18] John Wawrzynek,et al. Garp: a MIPS processor with a reconfigurable coprocessor , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[19] Chao Wang,et al. FPM: A Flexible Programming Model for MPSoC on FPGA , 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.
[20] Marco Platzner,et al. ReconOS: Multithreaded programming for reconfigurable computers , 2009, TECS.
[21] David H. Albonesi,et al. ReMAP: A Reconfigurable Heterogeneous Multicore Architecture , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[22] John Wawrzynek,et al. Research accelerator for multiple processors , 2006, 2006 IEEE Hot Chips 18 Symposium (HCS).
[23] Chao Wang,et al. SOMP: Service-Oriented Multi Processors , 2011, 2011 IEEE International Conference on Services Computing.
[24] Jim Stevens,et al. Hthreads: A Computational Model for Reconfigurable Devices , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[25] Chao Wang,et al. MP-Tomasulo: A Dependency-Aware Automatic Parallel Execution Engine for Sequential Programs , 2013, TACO.