论文信息 - A wide-range programmable high-speed CMOS frequency divider

A wide-range programmable high-speed CMOS frequency divider

We present a fully programmable frequency divider for high-speed CMOS applications. High degree of pipelining makes the maximum clock rate independent of the number of bits in the divider. A maximum operating frequency of 400 MHz has been measured on dividers implemented in a 1 /spl mu/m CMOS process.

Patrik Larsson | P. Larsson

[1] H.-I. Cong,et al. Multigigahertz CMOS dual-modulus prescaler IC , 1988 .

[2] Jiren Yuan. Efficient CMOS counter circuits , 1988 .

[3] Christer Svensson,et al. High-speed CMOS circuit technique , 1989 .

[4] C. Y. Ho,et al. A BiCMOS programmable frequency divider , 1992 .

[5] J. Yuan,et al. Novel carry propagation in high-speed synchronous counters and dividers , 1993 .

[6] Kiamal Pekmestzi,et al. Systolic frequency dividers/counters , 1994 .