Scaling the MOS transistor below 0.1 /spl mu/m: methodology, device structures, and technology requirements

This work is a systematic investigation of the feasibility of MOSFET's with a gate length below 0.1 /spl mu/m. Limits imposed on the scalability of oxide thickness and supply voltage require a new scaling methodology which allows these parameters to be maintained constant. The feasibility of achieving sub-0.1 /spl mu/m MOSFETs in this way is evaluated through simulations of the electrical characteristics of several different device structures and by addressing the most important issues related to the scaling down to ultra-short gate lengths. This study forms a valuable starting point for the understanding of technological requirements for future ULSI. >

[1]  D. Antoniadis,et al.  Reduction of channel hot-electron-generated substrate current in sub-150-nm channel length Si MOSFET's , 1988, IEEE Electron Device Letters.

[2]  T. Yoshitomi,et al.  Ultra-Shallow Buried-Channel P-MOSFET With Extremely High Transconductance , 1993, Symposium 1993 on VLSI Technology.

[3]  D. K. Ferry,et al.  Molecular-dynamics study of single-electron phenomena - impact of charge quantization on 1-100 nm Si-MOSFETs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[4]  D. Antoniadis,et al.  Physics and technology of ultra short channel MOSFET devices , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[5]  A. Kriman,et al.  Molecular dynamics extensions of Monte Carlo simulation in semiconductor device modeling , 1991 .

[6]  Shin Yokoyama,et al.  3 V Operation of 70 nm Gate Length MOSFET with New Double Punchthrough Stopper Structure , 1992 .

[7]  J. Barker,et al.  On the physics and modeling of small semiconductor devices—I , 1980 .

[8]  R. H. Storz,et al.  Clear observation of sub-band gap impact ionization at room temperature and below in 0.1 mu m Si MOSFETs , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[9]  B. Riccò,et al.  The impact of voltage scaling on electron heating and device performance of submicrometer MOSFETs , 1991 .

[10]  J. Colinge.  Silicon-on-Insulator Technology: Materials to VLSI , 1991 .

[11]  C. Fiegna,et al.  Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions , 1993, Proceedings of IEEE International Electron Devices Meeting.

[12]  Khan,et al.  Quantum corrections to the Boltzmann equation for transport in semiconductors in high electric fields. , 1986, Physical review. B, Condensed matter.

[13]  Y. Omura,et al.  0.1- mu m-gate, ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer , 1991 .

[14]  M. V. Fischetti,et al.  Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go? , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[15]  A. Toriumi,et al.  Hot-carrier effects in 0.1 mu m gate length CMOS devices , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[16]  Shinji Okazaki,et al.  0.1 mu m CMOS devices using low-impurity-channel transistors (LICT) , 1990, International Technical Digest on Electron Devices.

[17]  B. Riccò,et al.  A many-band silicon model for hot-electron transport at high energies , 1989 .

[18]  J.G. Fossum,et al.  Performance Limitations of Deep-Submicron Fully Depleted Soi Mosfet's , 1992, 1992 IEEE International SOI Conference.

[19]  C. Fiegna,et al.  Modeling of high-energy electrons in MOS devices at the microscopic level , 1993 .

[20]  S. Sze.  High-speed semiconductor devices , 1990 .

[21]  B. Riccò,et al.  An isotropic best-fitting band model for electron and hole transport in silicon , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[22]  T. Yoshitomi,et al.  An SPDD p-MOSFET structure suitable for 0.1 and sub 0.1 micron channel length and its electrical characteristics , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[23]  M. Sugiyama,et al.  BSA Technology for sub-100nm deep base bipolar transistors , 1987, 1987 International Electron Devices Meeting.

[24]  Naoyuki Shigyo,et al.  Effects of microscopic fluctuations in dopant distributions on MOSFET threshold voltage , 1992 .

[25]  F. Stern,et al.  Properties of Semiconductor Surface Inversion Layers in the Electric Quantum Limit , 1967 .

[26]  Yasuyuki Ohkura,et al.  Quantum effects in Si n-MOS inversion layer at high substrate concentration , 1990 .

[27]  Mark R. Pinto,et al.  Scaling the Si metal‐oxide‐semiconductor field‐effect transistor into the 0.1‐μm regime using vertical doping engineering , 1991 .