FPGA implementation of a 3GPP turbo codec

This paper describes the FPGA implementation of a 3GPP compliant TCC (turbo convolutional codes) codec. The decoder employs the MAP algorithm, utilizing the max* operator, and achieves a BER of 10/sup -6/ for a 1.5 dB SNR. In addition to providing an overview of the datapath architecture, the C based design and verification methodology is presented.

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