OPAIC: An optimization technique to improve energy consumption and performance in application specific network on chips

Abstract Network on Chip (NoC) is an appropriate and scalable solution for today’s System on Chips (SoCs) with the high communication demands. Application specific NoCs is preferable since they can be customized to optimize all requirements of the specific applications. This paper presents an OPtimization technique for Application specifIC NoCs (OPAIC), which aims not only to decrease the energy consumption but also to improve the area of NoCs. OPAIC is composed of three stages to find the optimum NoC; in the first stage, it uses a linearized form of a Quadratic Assignment Problem (QAP) to map tasks on cores to minimize the energy. In the second stage, a Mixed Integer Linear Problem (MILP) is proposed to find the optimum number of the routers for the layout earned in previous stage. Finally, a Greedy Algorithm is applied to optimize the number of virtual channel for every link based on its traffic needs.

[1]  Vincenzo Catania,et al.  Data Encoding Schemes in Networks on Chip , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Michal Czapinski,et al.  An effective Parallel Multistart Tabu Search for Quadratic Assignment Problem on CUDA platform , 2013, J. Parallel Distributed Comput..

[3]  Luca Benini,et al.  Networks on Chips: From research to products , 2010, Design Automation Conference.

[4]  Krishnan Srinivasan,et al.  An automated technique for topology and route generation of application specific on-chip interconnection networks , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[5]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[6]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  G. Paul,et al.  An efficient implementation of the robust tabu search heuristic for sparse quadratic assignment problems , 2010, Eur. J. Oper. Res..

[8]  Srinivasan Murali,et al.  A Methodology for Mapping Multiple Use-Cases onto Networks on Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[9]  Luca Benini.  Application Specific NoC Design , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[10]  Abdulkadir Sengur,et al.  GA-SELM: Greedy algorithms for sparse extreme learning machine , 2014 .

[11]  Krishnan Srinivasan,et al.  Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[12]  Krishnan Srinivasan,et al.  Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Krishnan Srinivasan,et al.  A technique for low energy mapping and routing in network-on-chip architectures , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[14]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[15]  Anelise Munaretto,et al.  GrAnt: Inferring best forwarders from complex networks' dynamics through a greedy Ant Colony Optimization , 2012, Comput. Networks.

[16]  L. Benini,et al.  Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[17]  W. Art Chaovalitwongse,et al.  An improved linearization technique for a class of quadratic 0-1 programming problems , 2012, Optim. Lett..

[18]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[19]  El-Ghazali Talbi,et al.  Metaheuristics - From Design to Implementation , 2009 .

[20]  Gerald Paul,et al.  Comparative performance of tabu search and simulated annealing heuristics for the quadratic assignment problem , 2010, Oper. Res. Lett..

[21]  Radu Marculescu,et al.  An Analytical Approach for Network-on-Chip Performance Analysis , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  L. Benini,et al.  /spl times/pipesCompiler: a tool for instantiating application specific networks on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[23]  W. Art Chaovalitwongse,et al.  A new linearization technique for multi-quadratic 0-1 programming problems , 2004, Oper. Res. Lett..

[24]  Li-Shiuan Peh,et al.  Leakage power modeling and optimization in interconnection networks , 2003, ISLPED '03.

[25]  Shaahin Hessabi,et al.  Low Power Encoding in NoCs Based on Coupling Transition Avoidance , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.