A test methodology for VLSI chips on silicon

This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multichip silicon substrate. After a brief description of the package technology itself, the necessary elements of an ideal test methodology are provided, along with a description of the drawbacks of existing methods. The test strategy developed, covering test from the wafer level, unpopulated substrate, and populated substrate, is then detailed.<<ETX>>

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