Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

A comprehensive tool has been implemented for the comparison of different test preparation techniques and target faults. It comprises of the realistic fault characterisation program LIFT that can extract sets of various faults from a given analogue or mixed-signal circuit layout and the automatic analogue fault simulation program AnaFAULT which can handle arbitrary catastrophic and parametric faults. For a fabricated integrated VCO circuit the capabilities of the tool are demonstrated and simulation results are presented.<<ETX>>

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