Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections

Current Field-Programmable Gate Arrays (FPGAs) are roughly three times slo wer and ten times less dense than Mask Programmed Gate Arrays (MPGAs) in the same VLSI technology . This speed and density dif ference arises mainly because of the slo w and lar ge programmable connections between FPGA logic blocks. One way to improve the speed and density of an FPGA is to substitute f ast and small fix ed metal connections, which we call hard-wired connections, between some of the primiti ve gates or basic blocks of an FPGA. We use hard-wired connections in FPGAs with hard-wired logic blocks (HLBs), where an HLB consists of se veral basic blocks connected by hard-wired connections. This dissertation describes algorithms for mapping basic block circuits to HLB circuits optimized for speed or area. HLB mapping is done in tw o steps: First, a co vering algorithm generates a set of HLBfragments to implement the input circuit. Second the co vering fragments are pack ed together to minimize the number of HLBs in the final HLB netlist. W e prove that the fragment covering algorithm, when optimizing delay , generates an HLB netlist with minimal number of programmable connections along critical paths. W e also prove sufficient conditions for the fragment packing algorithm to generate a minimal number of HLBs and sho w that all two-level HLB topologies satisfy these conditions. This dissertation e xplores a wide selection of LUT -based HLB FPGAs empirically . A suite of benchmark circuits is implemented in each HLB architecture and each circuit’ s area and delay is measured. The goal is to find the HLB architectures that will yield f ast FPGA circuits with reasonable density , and conversely, dense FPGA circuits with good speed. Since an HLB architecture is defined by its LUT size and its topology , the specific research questions are as follo ws: