Scalable and portable computing using the WPRAM model

Parallel machines are converging to a standard scalable architecture. A set of processors communicate through a network providing linear increases in bisection bandwidth, as the number of processors increase. Each processor also has a large local memory, providing linear increases in memory bandwidth. In addition, the support of uniform latencies removes the dependence of an algorithm on network locality to achieve good performance. It is widely believed that the widespread takeup of highly parallel machines can be aided by the provision of a standard computational model for the development and analysis of algorithms , leading to scalable and portable performance. This paper describes the recent research carried out using the WPRAM model. This aims to provide a small but exible set of operations which enables the implementation of highly concurrent algorithms with good practical performance. An associated cost system, targeted at the above class of machines, enables the analysis of alternative parallelisation methods, which can subsequently be \tuned" to the particular machine in use, for optimal performance.