Effective enforcement of path-delay constraints inperformance-driven placement

We propose a performance-driven cell placement method based on a modified force-directed approach. A pseudolink is added to connect the source and sink flip-flops of every critical path to enforce their closeness. Given user-specified input-output pad locations at the chip boundaries and starting with all core cells in the chip center, we iteratively move one cell at a time to its force-equilibrium location assuming all other cells are fixed. The process stops when no cell can be move farther than a threshold distance. Next, cell rows are formed one at a time starting from the top and bottom. After forming these two cell rows (top/bottom), all remaining movable core cells' force-equilibrium locations are updated. The row-formation-and-update process continues until all rows are formed and, hence, a legal placement is obtained. We have integrated the proposed approach into an industrial automatic placement-and-route flow. Experimental results on benchmark circuits up to 191-K cell (500-K gate) show that the critical path delay can be improved by as much as 17%. Our layout quality is independent of initial placement. We also study the effect on both layout quality and central processing unit time consumption due to the amount of pseudolinks added. We found that the introduction of pseudolink indeed significantly improves the layout quality. We also empirically demonstrated that the proposed approach is effective in reducing the total half-perimeter wirelength metric.

[1]  Frank M. Johannes,et al.  Performance optimization by interacting netlist transformations andplacement , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Pinaki Mazumder,et al.  VLSI cell placement techniques , 1991, CSUR.

[3]  Sachin S. Sapatnekar,et al.  An integrated algorithm for combined placement and libraryless technology mapping , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[4]  Frank M. Johannes,et al.  Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[5]  Majid Sarrafzadeh,et al.  Dragon2000: standard-cell placement tool for large industry circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[6]  Chung-Kuan Cheng,et al.  Module Placement Based on Resistive Network Optimization , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Jin Xu,et al.  Sequence-pair approach for rectilinear module placement , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  D. A. Mlynski,et al.  A Combined Force and Cut Algorithm for Hierarchical VLSI Layout , 1982, DAC 1982.

[9]  Pravin M. Vaidya,et al.  A performance driven macro-cell placement algorithm , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[10]  Robert K. Brayton,et al.  A force-directed macro-cell placer , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[11]  Wei Chen,et al.  Concurrent logic restructuring and placement for timing closure , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[12]  Youn-Long Lin,et al.  Integrating logic retiming and register placement , 1998, ICCAD '98.

[13]  Youn-Long Lin,et al.  A performance-driven standard-cell placer based on a modified force-directed algorithm , 2001, ISPD '01.

[14]  Shawki Areibi,et al.  Attractor-repeller approach for global placement , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[15]  Andrew B. Kahng,et al.  Faster minimization of linear wirelength for global placement , 1997, ISPD '97.

[16]  Neil R. Quinn.  The placement problem as viewed from the physics of classical mechanics , 1975, DAC '75.

[17]  Majid Sarrafzadeh,et al.  Congestion minimization during placement , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Wei Chen,et al.  Simultaneous gate sizing and placement , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Joseph R. Shinnerl,et al.  Multilevel optimization for large-scale circuit placement , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[20]  Sung-Woo Hur,et al.  Mongrel: hybrid techniques for standard cell placement , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[21]  Shantanu Dutt,et al.  Effective partition-driven placement with simultaneous level processing and global net views , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[22]  Massoud Pedram,et al.  Timing-driven placement based on partitioning with dynamic cut-net control , 2000, DAC.