A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS

Advanced communication systems require DACs with high linearity over a wide bandwidth while consuming low power and small area [1]-[6]. In this work, a 16b 6GS/s Nyquist current-steering DAC in 16nm CMOS is presented. Utilizing bounded INL calibration and thermometer DEM to tackle voltage and timing errors, this DAC achieves an INL<+/-0.25LSB, IMD<-90dBc up to 1.9GHz and SFDR>80dBc up to 900MHz while occupying an area of 0.52mm2 and dissipating 350mW from 1.0V and 3.0V supplies.

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[2]  Mike Shuo-Wei Chen,et al.  27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[3]  Anthony Collins,et al.  16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[4]  Harrie Gunnink,et al.  11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

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