Layout Vulnerability Reduction against Trojan Insertion Using Security-Aware White Space Distribution

Unwanted manipulation of layouts during the fabricating has been a major concern in current chip manufacturing process. Hardware Trojan insertion requires some resources such as white spaces and routing channels to place the Hardware Trojan components and maintain its connections. Conventional layout generation algorithms do not consider the security metrics during design cycle. In this paper, we proposed a metric to measure the vulnerability level of a layout against Trojan insertion. Then a new security-aware white space/congestion distribution algorithm is presented to reduce the vulnerability level of high risk regions of the layout. Experimental results show that more than 45% improvement in maximum vulnerability of layout in cost of less than 1% delay overhead.

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