Tools and Experimental Setup for Efficient Hardware Benchmarking of Candidates in Cryptographic Contests

Hardware benchmarking of candidates competing in cryptographic contests, such as SHA-3 and CAESAR, is very important for ranking of their suitability for standardization. The observed increase in the number of algorithms qualified to the first round of the respective contests (51 in case of SHA-3 and 57 for CAESAR) inevitably brings the question of the sustainability of the current approach, based on manual coding, and its applicability to the development of future cryptographic standards. A huge amount of time is necessary to design the datapath and controller and convert them to the hardware description language (HDL) code. The other difficulty is to develop a testbench in HDL for verification purposes. High-Level Synthesis (HLS), based on the newly developed Xilinx Vivado HLS tool, offers a potential solution to the aforementioned problems. Therefore, in the first part of this thesis we investigate the following hypothesis: Ranking of candidate algorithms in cryptographic contests in terms of their performance in modern FPGAs & AllProgrammable SoCs will remain the same independently whether the HDL implementations are developed manually or generated automatically using HLS tools.