Energy Estimation for Piecewise Regular Processor Arrays

In this paper, we present a rst approach for array-level energy estimation during high-level synthesis when mapping piecewise regular algorithms onto massively parallel full size processor arrays. In- nately, piecewise regular algorithms have some power consumption friendly properties, e.g., they may be mapped onto processor arrays with only lo- cal interconnect and memory. In addition to these properties, we show that the chosen mapping has a signicant inuence on the power con- sumption. Our energy estimation approach identies regions with de- creased switching activity of functional units' input operands. For these regions with reduced activity, a lower power consumption can be directly obtained from a generated table based model. Experimental results for- tify the accuracy and eciency of our methodology.

[1]  Jan M. Rabaey,et al.  Architectural power analysis: The dual bit type method , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Farid N. Najm,et al.  Power modeling for high-level power estimation , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Sujit Dey,et al.  High-Level Power Analysis and Optimization , 1997 .

[4]  Jürgen Teich,et al.  Synthesis of FPGA Implementations from Loop Algorithms , 2001 .

[5]  Paul Feautrier,et al.  Automatic Parallelization in the Polytope Model , 1996, The Data Parallel Programming Model.

[6]  R. Marculescu,et al.  Information theoretic measures for power analysis : Low power design , 1996 .

[7]  H. De Man,et al.  Global communication and memory optimizing transformations for low power signal processing systems , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[8]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[9]  Christian Lengauer,et al.  Loop Parallelization in the Polytope Model , 1993, CONCUR.

[10]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  J. Cortadella,et al.  Scheduling and resource binding for low power , 1995 .

[12]  Jürgen Teich,et al.  Scheduling of partitioned regular algorithms on processor arrays with constrained resources , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[13]  Niraj K. Jha,et al.  An ILP formulation for low power based on minimizing switched capacitance during data path allocation , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[14]  D.I. Moldovan,et al.  On the design of algorithms for VLSI systolic arrays , 1983, Proceedings of the IEEE.

[15]  Jordi Cortadella,et al.  High-level synthesis techniques for reducing the activity of functional units , 1995, ISLPED '95.

[16]  Lothar Thiele,et al.  Resource constrained scheduling of uniform algorithms , 1993, J. VLSI Signal Process..

[17]  Vincent Loechner,et al.  Parametric Analysis of Polyhedral Iteration Spaces , 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

[18]  Jürgen Teich.  A compiler for application specific processor arrays , 1993 .

[19]  Massoud Pedram,et al.  Module assignment for low power , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[20]  E. Ehrhart,et al.  Polynômes arithmétiques et méthode des polyèdres en combinatoire , 1974 .

[21]  Jürgen Teich,et al.  Design Space Exploration for Massively Parallel Processor Arrays , 2001, PaCT.

[22]  Hugo De Man,et al.  Global Communication and Memory Optimizing Transformations for Low Power Systems , 1994 .

[23]  Farid N. Najm,et al.  Power macro-models for DSP blocks with application to high-level synthesis , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).