Architectural implications of bit-level computation in communication applications

In this thesis, I explore a sub domain of computing, bit-level communication processing, which has traditionally only been implemented in custom hardware. Computing trends have shown that application domains previously implemented only in special purpose hardware are being moved into software on general purpose processors. If we assume that this trend continues, we must as computer architects reevaluate and propose new superior architectures for current and future application mixes. I believe that bit-level communication processing will be an important application area in the future and hence in this thesis I study several applications from this domain and how they map onto current computational architectures including microprocessors, tiled architectures, FPGAs, and ASICs. Unfortunately none of these architectures is able to efficiently handle bit-level communication processing along with general purpose computing. Therefore I propose a new architecture better suited to this task. Thesis Supervisor: Anant Agarwal Title: Professor of Electrical Engineering and Computer Science Acknowledgments I would like to thank Anant Agarwal for advising this thesis and imparting on me words of wisdom. Chris Batten was a great sounding board for my ideas and he helped me collect my thoughts before I started writing. I would like to thank Matthew Frank for helping me with the mechanics of how to write a thesis. I thank Jeffrey Cook and Douglas Armstrong who helped me sort my thoughts early on and reviewed drafts of this thesis. Jason E. Miller lent his photographic expertise by taking photos for my appendix. Walter Lee and Michael B. Taylor have been understanding officemates throughout this thesis and have survived my general crankiness over the summer of 2002. Mom and Dad have given me nothing but support through this thesis and my academic journey. Lastly I would like to thank DARPA, NSF, and Project Oxygen for funding this research.

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