A 3V CMOS 400mW 14b 1.4GS/s DAC for multi-carrier applications

This paper presents an uncalibrated 0.18 /spl mu/m CMOS 14 bit 1.4 GS/s DAC, with an LVDS interface, which achieves 67 dB SFDR for a 260 MHz full-scale tone and 70 dB ACLR for a two-carrier output, centered at 470 MHz. The IC dissipates a core power of 200 mW.

[1]  Tao Chen,et al.  Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[2]  C. C. McAndrew,et al.  Understanding MOSFET mismatch for analog design , 2003 .

[3]  Sungkyung Park,et al.  A digital-to-analog converter based on differential-quad switching , 2002, IEEE J. Solid State Circuits.

[4]  H. Amishiro,et al.  A 350-MS/s 3.3-V 8-bit CMOS D/A converter using a delayed driving scheme , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[5]  W. Sansen,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).