A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs

To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

[1]  D. Bortolato,et al.  Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[2]  Heather Quinn,et al.  Radiation-Induced Multi-Bit Upsets in Xilinx SRAM-Based FPGAs , .

[3]  Charles E. Stroud,et al.  Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[4]  P. K. Lala.  Self-Checking and Fault-Tolerant Digital Design , 1995 .

[5]  Maya Gokhale,et al.  Dynamic reconfiguration for management of radiation-induced faults in FPGAs , 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

[6]  Massimo Violante,et al.  Simulation-based analysis of SEU effects in SRAM-based FPGAs , 2004, IEEE Transactions on Nuclear Science.

[7]  Michael J. Wirthlin,et al.  The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[8]  D. Bortolato,et al.  Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs” , 2003 .

[9]  Massimo Violante,et al.  A new reliability-oriented place and route algorithm for SRAM-based FPGAs , 2006, IEEE Transactions on Computers.

[10]  Gustavo Ribeiro Alves,et al.  A self-healing real-time system based on run-time self-reconfiguration , 2005, 2005 IEEE Conference on Emerging Technologies and Factory Automation.

[11]  Gustavo Ribeiro Alves,et al.  Active replication: towards a truly SRAM-based FPGA on-line concurrent testing , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[12]  E. Fuller,et al.  RADIATION TESTING UPDATE, SEU MITIGATION, AND AVAILABILITY ANALYSIS OF THE VIRTEX FPGA FOR SPACE RECONFIGURABLE COMPUTING. , 2000 .

[13]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[14]  Luigi Carro,et al.  On the optimal design of triple modular redundancy logic for SRAM-based FPGAs , 2005, Design, Automation and Test in Europe.

[15]  C. Carmichael,et al.  Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs) , 2004, IEEE Transactions on Nuclear Science.

[16]  M. Caffrey,et al.  SEU Mitigation Techniques for Virtex FPGAs in Space Applications , 1999 .

[17]  R. Leveugle,et al.  Using run-time reconfiguration for fault injection applications , 2001, IMTC 2001. Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference. Rediscovering Measurement in the Age of Informatics (Cat. No.01CH 37188).

[18]  Li Wang,et al.  Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit , 2005 .

[19]  L. Sterpone,et al.  Analysis of the robustness of the TMR architecture in SRAM-based FPGAs , 2005, IEEE Transactions on Nuclear Science.

[20]  Delon Levi,et al.  JBits: Java based interface for reconfigurable computing , 1999 .