A Low-Power Architecture for the Design of a One-Dimensional Median Filter

This brief presents a low-power architecture for the design of a one-dimension median filter. It is a word-level two-stage pipelined filter, receiving an input sample and generating a median output at each machine cycle. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the stored samples immobile in the window through the use of a token ring in our architecture. The experimental results have shown that, at the expense of some additional area cost, the power consumption can be successfully reduced.

[1]  Lukás Sekanina,et al.  Novel Hardware Implementation of Adaptive Median Filters , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[2]  Chun-Hsien Yeh,et al.  Design of an Area-Efficient One-Dimensional Median Filter , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Massoud Pedram,et al.  BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Robert Simon Sherratt,et al.  Fast median calculation method , 2012 .

[5]  Dana S. Richards,et al.  VLSI median filters , 1990, IEEE Trans. Acoust. Speech Signal Process..

[6]  Oscal T.-C. Chen,et al.  Minimization of switching activities of partial products for designing low-power multipliers , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Alain Greiner,et al.  Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[8]  Chang Choo,et al.  A real-time bit-serial rank filter implementation using Xilinx FPGA , 2008, Electronic Imaging.

[9]  Steven M. Nowick,et al.  Robust interfaces for mixed-timing systems , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Wayne Luk,et al.  High-throughput one-dimensional median and weighted median filters on FPGA , 2009, IET Comput. Digit. Tech..

[11]  Dragana Prokin,et al.  Low Hardware Complexity Pipelined Rank Filter , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Vasily G. Moshnyaga,et al.  An efficient implementation of 1-D median filter , 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.