Interactive presentation: Reliability-aware system synthesis

Increasing reliability is one of the most important design goals for current and future embedded systems. In this paper, we will put focus on the design phase in which reliability constitutes one of several competing design objectives. Existing approaches considered the simultaneous optimization of reliability with other objectives to be too extensive. Hence, they firstly design a system, secondly analyze the system for reliability and finally exchange critical parts or introduce redundancy in order to satisfy given reliability constraints or optimize reliability. Unfortunately, this may lead to suboptimal designs concerning other design objectives. Here, we will present a) a novel approach that considers reliability with all other design objectives simultaneously, b) an evaluation technique that is able to perform a quantitative analysis in reasonable time even for real-world applications, and c) experimental results showing the effectiveness of our approach.

[1]  Martin Lukasiewycz,et al.  Improving system level design space exploration by incorporating SAT-solvers into multi-objective evolutionary algorithms , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[2]  Jürgen Teich,et al.  System-Level Synthesis Using Evolutionary Algorithms , 1998, Des. Autom. Embed. Syst..

[3]  Ramesh Karri,et al.  Transformation-based high-level synthesis of fault-tolerant ASICs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[4]  Lothar Thiele,et al.  Chapter 4 – Design Space Exploration of Network Processor Architectures , 2003 .

[5]  Mary Jane Irwin,et al.  Reliability-aware co-synthesis for embedded systems , 2004 .

[6]  David W. Coit,et al.  Reliability optimization of series-parallel systems using a genetic algorithm , 1996, IEEE Trans. Reliab..

[7]  Marco Laumanns,et al.  PISA: A Platform and Programming Language Independent Interface for Search Algorithms , 2003, EMO.

[8]  Luigi Carro,et al.  Designing and testing fault-tolerant techniques for SRAM-based FPGAs , 2004, CF '04.

[9]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[10]  Mahmut T. Kandemir,et al.  Reliability-centric high-level synthesis , 2005, Design, Automation and Test in Europe.

[11]  Alessandro Birolini.  Reliability Engineering: Theory and Practice , 1999 .

[12]  Donatella Sciuto,et al.  Reliability Properties Assessment at System Level: A Co-Design Framework , 2002 .

[13]  Shuvra S. Bhattacharyya,et al.  CHARMED: a multi-objective co-synthesis framework for multi-mode embedded systems , 2004 .

[14]  Antoine Rauzy,et al.  New algorithms for fault trees analysis , 1993 .