SoftContract: Model-Based Design of Error-Checking Code and Property Monitors

This paper discusses a model-based design flow for requirements in distributed embedded software development. Such requirements are specified using a language similar to Linear Temporal Logic which allows one to reason about time and sequencing. They consist of assertions which must hold for a design, given some assumptions on its environment. They can be checked both during simulation and, at least for a subset, even on the target. Of course the guarantee of correctness is ensured only as long as the assertion express the complete design intent, and the simulation stimuli cover all possible cases. While this is generally not true, the simulation-based approach is a practical manner to ensure correctness with a good degree of confidence, while avoiding the intricacies of software formal verification. Assertions related to deadline satisfaction can also be checked statically by a schedulability analysis tool. The key contribution of the paper is the extension to the embedded software domain of assertion-based verification, and the automated generation of property-checking code in multiple target languages, from simulation, to prototyping, to final production.