Highly secured state-shift local clock circuit to countermeasure against side channel attack

We propose a highly-secured State-shift Local Clock (SsLC) countermeasure technique to hide the Physical Leakage Information (PLI) against Side Channel Attack (SCA). The SCA is a technique employed to reveal the secret key of cryptographic algorithm by correlating the PLI (i.e. power dissipation and Electromagnetic (EM)) with the processed data, where both the PLI and processed data are generated during the encryption process. Whereas the countermeasure technique aims to reduce the correlation of the PLI against the processed data. There are four key features in our proposed SsLC countermeasure technique. First, it embodies a finite state machine which can be employed to regularly shift the timing operation of cryptographic algorithm implementations. Thus, the correlation of the PLI with the processed data is significantly reduced due to dynamically changes the occurrences of encryption operation in time domain. Second, the PLI which encompasses a secret key is spread over in time domain to reduce the probability of revealing the secret key. Third, the power dissipation overhead is negligible and hence it is highly applicable for low power applications. Fourth, the regular state (time) shifting technique in the SsLC is able to hide multiple PLIs, i.e. power dissipation and EM signals, concurrently. In view of the above features, the proposed SsLC is highly secured against SCA with multiple PLIs. Based on the experimental results in FPGA, our proposed SsLC countermeasure technique features wide distribution of PLI in time domain, dissipates 2.77mW of power and emits 12.2mV/m of EM signal @ 2.4MHz. Furthermore, with 106 power dissipation and EM measurements, the secret key of the cryptographic algorithm remains unbreakable. In comparison with the reported counterparts, the resistance of our proposed SsLC against SCA is significantly improved as the number of power dissipation and EM traces to reveal the secret key has increased by >18x and >25x respectively. Consequently, the correlation coefficient between the PLI and the processed data is reduced by 3.5x.