Area and time co-optimization for system-on-a-chip based on consecutive testability

This paper presents an area overhead and test time cooptimization method for SoCs based on consecutive testability. Consecutive testability of SoCs guarantees that we can handle any test sequence that requires consecutive application of test patterns at speed of system clock such as a test sequence for timing faults. The proposed method creates a test schedule and TAM using existing interconnects as much as possible. Moreover, the method allows tradeoff between area overhead and test time according to user defined ratio. Experimental results show that the proposed method can achieve lower area overhead compared to test bus architecture due to the utilization of existing interconnects as a part of TAM. keywords: system-on-a-chip, design for testability, test access mechanism, test scheduling, consecutive testability

[1]  Krishnendu Chakrabarty.  Design of system-on-a-chip test access architectures using integer linear programming , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[2]  Yervant Zorian,et al.  Testing embedded-core based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[3]  Krishnendu Chakrabarty.  Design of system-on-a-chip test access architectures under place-and-route and power constraints , 2000, Proceedings 37th Design Automation Conference.

[4]  Krishnendu Chakrabarty,et al.  Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[5]  Srivaths Ravi,et al.  Testing of core-based systems-on-a-chip , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Erik Jan Marinissen,et al.  A structured and scalable mechanism for test access to embedded reusable cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  Hideo Fujiwara,et al.  Design for consecutive transparency of cores in system-on-a-chip , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[8]  Hideo Fujiwara,et al.  Integrated test scheduling, test parallelization and TAM design , 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

[9]  Prab Varma,et al.  A structured test re-use methodology for core-based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[10]  Lee Whetsel,et al.  An IEEE 1149.1 based test access architecture for ICs with embedded cores , 1997, Proceedings International Test Conference 1997.

[11]  Christos A. Papachristou,et al.  Structural Fault Testing of Embedded Cores Using Pipelining , 1999, J. Electron. Test..

[12]  Prab Varma,et al.  A unifying methodology for intellectual property and custom logic testing , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[13]  Yoshiyuki Nakamura,et al.  Integrated and automated design-for-testability implementation for cell-based ICs , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[14]  Nur A. Touba,et al.  Testing embedded cores using partial isolation rings , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[15]  Hideo Fujiwara,et al.  Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores , 2002, J. Electron. Test..

[16]  Sujit Dey,et al.  A fast and low-cost testing technique for core-based system-chips , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  J. Huisman.  The Netherlands , 1996, The Lancet.

[18]  Krishnendu Chakrabarty,et al.  Synthesis of transparent circuits for hierarchical and system-on-a-chip test , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.